1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems incorporating debug mechanisms and the manner in which such systems execute debug instructions.
2. Description of the Prior Art
In order to facilitate the development of new data processing hardware and software it is known to provide dedicated debug mechanisms. Such mechanisms typically allow diagnostic data to be recovered and debug instructions to be executed, such as instructions to recover certain data values to locations from which they can be accessed as diagnostic data. In addition, it may be desired to execute particular instructions that use particular features or portions of the system being debugged to test the operation of those particular features or portions.
Some known data processing systems operate in the debug mode by switching to a different clock speed (typically slower) than the normal operation clock speed and then loading the desired instruction or instructions to be executed whilst remaining at the different clock speed. Whilst the different clock speed facilitates the loading of the instructions into the system (for example via a serial scan chain), it has the disadvantage that the instruction is not executed at its normal speed and so the value of the diagnostic operation is reduced.
Other known systems address this problem by loading the instructions at the different clock speed and then switching to the full clock speed for execution of that instruction before switching back to the different clock speed. Whilst this improves the accuracy and usefulness of the diagnostic operation, it has the disadvantage of requiring switching between clock speeds, clock synchronisation and their associated circuits.